The present embodiments relate to static timing analysis, and more specifically to using variable accuracy parameter modeling in statistical static timing analysis.
One form of performance analysis that is used during integrated circuit (IC) design is static timing analysis (STA). Static timing analysis identifies circuit races/hazards that could cause a chip to malfunction, verifies the operational speed of a chip, and identifies the paths, which limit the operational speed of the integrated circuit. Static timing analysis typically operates on a timing graph, in which graph nodes represent electrical nodes (e.g., circuit pins) where signals may make transitions at various times; and in which graph edges, or segments, representing the delays of the circuits and/or wires connecting the nodes. Although static timing analysis may report performance-limiting paths, typical static timing analysis methods may not actually operate on paths (of which there may be an exponentially large number), and instead can be “block-based” to compute and propagate forward signal arrival times reflecting the earliest and/or latest possible times that signal transitions can occur at nodes in the timing graph. As a result, static timing analysis is efficient, allowing for rapid estimation of circuit timing on very large designs as compared to other approaches (e.g., transient simulation).
One aspect of static timing analysis is evaluation of timing tests, which are ordering relationships between the arrival times of signals on converging paths. These are often represented in a timing graph as test edges, or segments. Common examples of timing tests are setup tests, requiring that a data signal at an input of a flip-flop or other memory element becomes stable for some setup period before the clock signal transition that stores that data (i.e., that the latest possible data transition in a clock cycle occur at least the required setup period before the earliest possible clock transition for that cycle); and hold tests, requiring that a data signal at an input of a flip-flop or other memory element remain stable for some hold period before the clock signal transition that stores that data (i.e., that the earliest possible data transition in a clock cycle occur at least the required hold period after the latest possible clock transition for the preceding clock cycle). Pairs of paths along which early and late arrival times compared in a timing test are propagated are often referred to as racing paths.
It is commonly recognized that electrical characteristics of transistors and interconnects are not the same for different IC chips and even for the same chip at different periods of time or chip locations. Variation of electrical characteristics can be due to variation of process parameters, changing of environmental conditions and even chip age (e.g., Hot Carriers Injections, Negative Bias Temperature Instability, electromigration, and so forth). The variation of electrical characteristics results in variations of gate timing characteristics. Traditional deterministic static timing analysis may typically be performed at a particular “corner,” which is a specified combination of conditions such as voltage, temperature, and manufacturing process (PVT) that affect delays of circuits on a chip. However, the timing results can vary widely between corners as changes in temperature, voltage, process, etc., can have a strong affect on the delays through the chip components. The traditional conservative way to handle these variations is to perform multiple static timing analysis runs at all so-called process corners at which the gates may have the worst combinations of delays, sometimes referred to as base corners. In other words, base corners may be best case, nominal, and worst case settings for variables (such as PVT, etc.). Then chips are designed so that they can properly function at all process corners assuming that as a result they will function at any other combination of gate delays.
However, with decreasing transistor size and interconnect width, the variation of electrical characteristics is becoming proportionally larger. Therefore, the multi-corner analysis approach results in too conservative and non-optimal designs because most design efforts and chip resources are spent to make chips function at very low-probability combinations of electrical characteristics. Additionally, the fixing of failed timing tests in one process corner may lead to new timing test failures in other corners, requiring a costly iterative design process. An alternative approach to designing chips is to consider actual statistical characteristics of process parameter variations and use them to compute statistical characteristics of a designed circuit. This approach is referred to as the Statistical Static Timing Analysis (SSTA) approach.
There are various categories of SSTA processes: path-based and block-based methods. A path-based SSTA process sums gate and wire delays on specific paths. The statistical calculation uses less computing resources, but the paths of interest are identified prior to running the analysis, which takes time, and there is the potential that some other paths may be relevant but not analyzed so path selection is important. A block-based SSTA process generates the arrival times for each node, working from the clocked elements. The advantage of a block-based SSTA process is completeness, and there is no need for path selection. One issue with SSTA is that a statistical max (or min) operation, that also considers correlation, would be useful; however, this is a difficult technical problem to achieve.
Statistical static timing analysis explicitly propagates mean timing values and sensitivities of these mean timing values to sources of variation through the timing graph, based on modeled variability information contained in asserted timing constraints and the delay models. These sensitivities may then cancel when arrival time differences are computed at test slack calculation time, providing pessimism reduction during the original block based timing analysis. Statistical min/max operations are used to compute the early and late mode arrival times, respectively, when paths converge, including computing both new mean values and sensitivities to various parameters. As the distributions propagated represent functions rather than discrete numerical values, operations such as addition and subtraction, and in particular max and min, can be very computationally extensive and expensive as compared to traditional deterministic timing. Regardless of the timing approach used, the runtime required to perform timing analysis impacts the number of design iterations, and there is strong interest in keeping the runtime to a minimum. Therefore, methods that can reduce runtime while maintaining timing accuracy are desirable.
Thus, sensitivities are computed for every timing quantity. Typically this is done with the finite-difference technique, and includes: rise/fall/early/late for delay, slew, and for each statistical source of variation. This also gets multiplied for each unique clock/phase and propagated. Also, SSTA uses a canonical model to analyze variation. The vector of data within the canonical model can be computationally expensive to create, store, and propagate, which results in an increase in runtime and memory requirements.